(China (Mainland))
Product Summary
The PA7572JI-20 is a member of the Programmable Electrically Erasable Logic (PEEL) Array family based on Anachip CMOS EEPROM technology. PEEL Arrays free designers from the limitations of ordinary PLDs by providing the architectural flexibility and speed needed for today programmable logic designs. The PA7572JI-20 offers a versatile logic array architecture with 24 I/O pins, 14 input pins and 60 registers/latches (24 buried logic cells, 12 input registers/latches, 24 buried I/O registers/latches). Its logic array implements 100 sum-of-products logic functions divided into two groups each serving 12 logic cells. Each group shares half (60) of the 120 product-terms available.
Parametrics
PA7572JI-20 absolute maximum ratings: (1)Supply Voltage Relative to Ground: -0.5 to + 7.0 V; (2)Voltage Applied to Any Pin Relative to Ground1: -0.5 to VCC + 0.6 V; (3)Output Current Per pin (IOL, IOH): ±25 mA ; (4)Storage Temperature: -65 to + 150℃; (5)Lead Temperature Soldering 10 seconds: +300℃.
Features
PA7572JI-20 features: (1)Versatile Logic Array Architecture; (2)High-Speed Commercial and Industrial Versions; (3)Ideal for Combinatorial, Synchronous and Asynchronous Logic Applications; (4)CMOS Electrically Erasable Technology; (5)Flexible Logic Cell; (6)Development and Programmer Support.
Diagrams
| Image | Part No | Mfg | Description |  |
Pricing (USD) |
Quantity | ||||
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 |
 PA7572JI-20 |
Diodes Inc. |
CPLD - Complex Programmable Logic Devices 14 INP 24 I/O 20ns |
Data Sheet |
Negotiable |
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PA7572JI-20L |
Diodes Inc. |
CPLD - Complex Programmable Logic Devices 14 Input 24 I/O 20ns |
Data Sheet |
Negotiable |
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